1. Field of the Invention
The present invention relates to a data decoding apparatus for decoding compression-encoded video data with a low delay and at a high speed, the compression-encoded video data being obtained by compression-encoding a video image in accordance a video encoding scheme as represented by an MPEG scheme employing Discrete Cosine Transformation (DCT).
2. Description of the Related Art
Conventionally, it has been well known that an MPEG video decoder is employed as a data decoding apparatus for decoding, with a comparatively low delay, video data compression-encoded based on an MPEG (Moving Picture Experts Group) scheme in conformance with International Standards for Moving Picture Encoding.
In the conventional data decoding apparatus, input compression-encoded video data is decoded through a syntax interpreter, a variable length decoder, a dequantizer, a zero-run reconstruction device, a block buffer, an inverse discrete cosine transformer, a micro-block buffer, and a motion compensator. The block buffer is employed to temporarily stores the reconstruction result of the zero-run reconstruction device, and output it in order of coefficients suitable to processing by means of the rear stage inverse discrete cosine transformer for each block. The macro-block buffer is employed to carry out processing of the motion compensator in units of a plurality of blocks. The decoding result of the variable length decoder inputs to a parameter decoder as well, and a parameter required for the block buffer is extracted.
However, in this decoding processor, processing at the zero-run reconstruction device is carried out in units of blocks. In a block with the small number of nonzero coefficients, decoding process for each block terminates within a short period of time. Thus, there is a problem that processing of the variable length decoder arranged at the front stage of the zero-run reconstruction device stops frequently every block, a standby time is increased until next processing has been enabled at the syntax interpreter or parameter decoder, and a processing speed is lowered.
Therefore, in particular, in the case where an attempt is made to decode compression-encoded data with a high encoding rate such as a high definition digital TV broadcast signal, it is required to terminate processing in units of blocks within a short period of time. Thus, it is required to speed up processing of a majority of processors of the data decoding apparatus in order to compensate for the lowered processing efficiency of this variable length decoder. As a result, the circuit scale of the entire apparatus is increased, and power consumption is increased.
As has been described above, in the conventional data decoding apparatus, the entire processing speed is slower due to the lowered processing efficiency of the variable length decoder. Therefore, in the case where an attempt is made to decode compression-encoded data with a high encoding rate, it is required to speed up the processing of a majority of processors of the apparatus. Thus, there has been a problem that the circuit scale and power consumption are increased.